\doxysubsubsubsection{RCCEx CRS Synchro\+Divider }
\hypertarget{group___r_c_c_ex___c_r_s___synchro_divider}{}\label{group___r_c_c_ex___c_r_s___synchro_divider}\index{RCCEx CRS SynchroDivider@{RCCEx CRS SynchroDivider}}
\doxysubsubsubsubsubsection*{Macros}
\begin{DoxyCompactItemize}
\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___c_r_s___synchro_divider_ga60aae5d8cd38a3ace894df002aa14a14}{RCC\+\_\+\+CRS\+\_\+\+SYNC\+\_\+\+DIV1}}~(0x00000000U)
\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___c_r_s___synchro_divider_ga2f75c52f4ac93c112c8bb76943ed7ccc}{RCC\+\_\+\+CRS\+\_\+\+SYNC\+\_\+\+DIV2}}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga386136633d2d7330e0ac5ca183c292de}{CRS\+\_\+\+CFGR\+\_\+\+SYNCDIV\+\_\+0}}
\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___c_r_s___synchro_divider_gacd65fae74865d415912220f0db616f56}{RCC\+\_\+\+CRS\+\_\+\+SYNC\+\_\+\+DIV4}}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gae595c852cabc78e8bc9055625d68ca54}{CRS\+\_\+\+CFGR\+\_\+\+SYNCDIV\+\_\+1}}
\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___c_r_s___synchro_divider_gad2bd5dac3b5d22a86bc3c8d9a355768a}{RCC\+\_\+\+CRS\+\_\+\+SYNC\+\_\+\+DIV8}}~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_gae595c852cabc78e8bc9055625d68ca54}{CRS\+\_\+\+CFGR\+\_\+\+SYNCDIV\+\_\+1}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga386136633d2d7330e0ac5ca183c292de}{CRS\+\_\+\+CFGR\+\_\+\+SYNCDIV\+\_\+0}})
\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___c_r_s___synchro_divider_ga6f30090710f3722cc59e7b7d4c079781}{RCC\+\_\+\+CRS\+\_\+\+SYNC\+\_\+\+DIV16}}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa7a4d4b65dbf3623f93cf14ed953fd42}{CRS\+\_\+\+CFGR\+\_\+\+SYNCDIV\+\_\+2}}
\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___c_r_s___synchro_divider_ga1c41b5ff0a49c91a3bdf281273d22618}{RCC\+\_\+\+CRS\+\_\+\+SYNC\+\_\+\+DIV32}}~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa7a4d4b65dbf3623f93cf14ed953fd42}{CRS\+\_\+\+CFGR\+\_\+\+SYNCDIV\+\_\+2}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga386136633d2d7330e0ac5ca183c292de}{CRS\+\_\+\+CFGR\+\_\+\+SYNCDIV\+\_\+0}})
\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___c_r_s___synchro_divider_gad5d81304197848a0f790cf52ad3280d8}{RCC\+\_\+\+CRS\+\_\+\+SYNC\+\_\+\+DIV64}}~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa7a4d4b65dbf3623f93cf14ed953fd42}{CRS\+\_\+\+CFGR\+\_\+\+SYNCDIV\+\_\+2}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_gae595c852cabc78e8bc9055625d68ca54}{CRS\+\_\+\+CFGR\+\_\+\+SYNCDIV\+\_\+1}})
\item 
\#define \mbox{\hyperlink{group___r_c_c_ex___c_r_s___synchro_divider_ga10c555a684def76ffe90d24070a3216b}{RCC\+\_\+\+CRS\+\_\+\+SYNC\+\_\+\+DIV128}}~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gad0b3ee2ab042802997e57d788c640647}{CRS\+\_\+\+CFGR\+\_\+\+SYNCDIV}}
\end{DoxyCompactItemize}


\doxysubsubsubsubsection{Detailed Description}


\label{doc-define-members}
\Hypertarget{group___r_c_c_ex___c_r_s___synchro_divider_doc-define-members}
\doxysubsubsubsubsection{Macro Definition Documentation}
\Hypertarget{group___r_c_c_ex___c_r_s___synchro_divider_ga60aae5d8cd38a3ace894df002aa14a14}\index{RCCEx CRS SynchroDivider@{RCCEx CRS SynchroDivider}!RCC\_CRS\_SYNC\_DIV1@{RCC\_CRS\_SYNC\_DIV1}}
\index{RCC\_CRS\_SYNC\_DIV1@{RCC\_CRS\_SYNC\_DIV1}!RCCEx CRS SynchroDivider@{RCCEx CRS SynchroDivider}}
\doxysubsubsubsubsubsection{\texorpdfstring{RCC\_CRS\_SYNC\_DIV1}{RCC\_CRS\_SYNC\_DIV1}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___c_r_s___synchro_divider_ga60aae5d8cd38a3ace894df002aa14a14} 
\#define RCC\+\_\+\+CRS\+\_\+\+SYNC\+\_\+\+DIV1~(0x00000000U)}

Synchro Signal not divided (default) \Hypertarget{group___r_c_c_ex___c_r_s___synchro_divider_ga10c555a684def76ffe90d24070a3216b}\index{RCCEx CRS SynchroDivider@{RCCEx CRS SynchroDivider}!RCC\_CRS\_SYNC\_DIV128@{RCC\_CRS\_SYNC\_DIV128}}
\index{RCC\_CRS\_SYNC\_DIV128@{RCC\_CRS\_SYNC\_DIV128}!RCCEx CRS SynchroDivider@{RCCEx CRS SynchroDivider}}
\doxysubsubsubsubsubsection{\texorpdfstring{RCC\_CRS\_SYNC\_DIV128}{RCC\_CRS\_SYNC\_DIV128}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___c_r_s___synchro_divider_ga10c555a684def76ffe90d24070a3216b} 
\#define RCC\+\_\+\+CRS\+\_\+\+SYNC\+\_\+\+DIV128~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gad0b3ee2ab042802997e57d788c640647}{CRS\+\_\+\+CFGR\+\_\+\+SYNCDIV}}}

Synchro Signal divided by 128 \Hypertarget{group___r_c_c_ex___c_r_s___synchro_divider_ga6f30090710f3722cc59e7b7d4c079781}\index{RCCEx CRS SynchroDivider@{RCCEx CRS SynchroDivider}!RCC\_CRS\_SYNC\_DIV16@{RCC\_CRS\_SYNC\_DIV16}}
\index{RCC\_CRS\_SYNC\_DIV16@{RCC\_CRS\_SYNC\_DIV16}!RCCEx CRS SynchroDivider@{RCCEx CRS SynchroDivider}}
\doxysubsubsubsubsubsection{\texorpdfstring{RCC\_CRS\_SYNC\_DIV16}{RCC\_CRS\_SYNC\_DIV16}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___c_r_s___synchro_divider_ga6f30090710f3722cc59e7b7d4c079781} 
\#define RCC\+\_\+\+CRS\+\_\+\+SYNC\+\_\+\+DIV16~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa7a4d4b65dbf3623f93cf14ed953fd42}{CRS\+\_\+\+CFGR\+\_\+\+SYNCDIV\+\_\+2}}}

Synchro Signal divided by 16 \Hypertarget{group___r_c_c_ex___c_r_s___synchro_divider_ga2f75c52f4ac93c112c8bb76943ed7ccc}\index{RCCEx CRS SynchroDivider@{RCCEx CRS SynchroDivider}!RCC\_CRS\_SYNC\_DIV2@{RCC\_CRS\_SYNC\_DIV2}}
\index{RCC\_CRS\_SYNC\_DIV2@{RCC\_CRS\_SYNC\_DIV2}!RCCEx CRS SynchroDivider@{RCCEx CRS SynchroDivider}}
\doxysubsubsubsubsubsection{\texorpdfstring{RCC\_CRS\_SYNC\_DIV2}{RCC\_CRS\_SYNC\_DIV2}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___c_r_s___synchro_divider_ga2f75c52f4ac93c112c8bb76943ed7ccc} 
\#define RCC\+\_\+\+CRS\+\_\+\+SYNC\+\_\+\+DIV2~\mbox{\hyperlink{group___peripheral___registers___bits___definition_ga386136633d2d7330e0ac5ca183c292de}{CRS\+\_\+\+CFGR\+\_\+\+SYNCDIV\+\_\+0}}}

Synchro Signal divided by 2 \Hypertarget{group___r_c_c_ex___c_r_s___synchro_divider_ga1c41b5ff0a49c91a3bdf281273d22618}\index{RCCEx CRS SynchroDivider@{RCCEx CRS SynchroDivider}!RCC\_CRS\_SYNC\_DIV32@{RCC\_CRS\_SYNC\_DIV32}}
\index{RCC\_CRS\_SYNC\_DIV32@{RCC\_CRS\_SYNC\_DIV32}!RCCEx CRS SynchroDivider@{RCCEx CRS SynchroDivider}}
\doxysubsubsubsubsubsection{\texorpdfstring{RCC\_CRS\_SYNC\_DIV32}{RCC\_CRS\_SYNC\_DIV32}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___c_r_s___synchro_divider_ga1c41b5ff0a49c91a3bdf281273d22618} 
\#define RCC\+\_\+\+CRS\+\_\+\+SYNC\+\_\+\+DIV32~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa7a4d4b65dbf3623f93cf14ed953fd42}{CRS\+\_\+\+CFGR\+\_\+\+SYNCDIV\+\_\+2}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga386136633d2d7330e0ac5ca183c292de}{CRS\+\_\+\+CFGR\+\_\+\+SYNCDIV\+\_\+0}})}

Synchro Signal divided by 32 \Hypertarget{group___r_c_c_ex___c_r_s___synchro_divider_gacd65fae74865d415912220f0db616f56}\index{RCCEx CRS SynchroDivider@{RCCEx CRS SynchroDivider}!RCC\_CRS\_SYNC\_DIV4@{RCC\_CRS\_SYNC\_DIV4}}
\index{RCC\_CRS\_SYNC\_DIV4@{RCC\_CRS\_SYNC\_DIV4}!RCCEx CRS SynchroDivider@{RCCEx CRS SynchroDivider}}
\doxysubsubsubsubsubsection{\texorpdfstring{RCC\_CRS\_SYNC\_DIV4}{RCC\_CRS\_SYNC\_DIV4}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___c_r_s___synchro_divider_gacd65fae74865d415912220f0db616f56} 
\#define RCC\+\_\+\+CRS\+\_\+\+SYNC\+\_\+\+DIV4~\mbox{\hyperlink{group___peripheral___registers___bits___definition_gae595c852cabc78e8bc9055625d68ca54}{CRS\+\_\+\+CFGR\+\_\+\+SYNCDIV\+\_\+1}}}

Synchro Signal divided by 4 \Hypertarget{group___r_c_c_ex___c_r_s___synchro_divider_gad5d81304197848a0f790cf52ad3280d8}\index{RCCEx CRS SynchroDivider@{RCCEx CRS SynchroDivider}!RCC\_CRS\_SYNC\_DIV64@{RCC\_CRS\_SYNC\_DIV64}}
\index{RCC\_CRS\_SYNC\_DIV64@{RCC\_CRS\_SYNC\_DIV64}!RCCEx CRS SynchroDivider@{RCCEx CRS SynchroDivider}}
\doxysubsubsubsubsubsection{\texorpdfstring{RCC\_CRS\_SYNC\_DIV64}{RCC\_CRS\_SYNC\_DIV64}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___c_r_s___synchro_divider_gad5d81304197848a0f790cf52ad3280d8} 
\#define RCC\+\_\+\+CRS\+\_\+\+SYNC\+\_\+\+DIV64~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_gaa7a4d4b65dbf3623f93cf14ed953fd42}{CRS\+\_\+\+CFGR\+\_\+\+SYNCDIV\+\_\+2}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_gae595c852cabc78e8bc9055625d68ca54}{CRS\+\_\+\+CFGR\+\_\+\+SYNCDIV\+\_\+1}})}

Synchro Signal divided by 64 \Hypertarget{group___r_c_c_ex___c_r_s___synchro_divider_gad2bd5dac3b5d22a86bc3c8d9a355768a}\index{RCCEx CRS SynchroDivider@{RCCEx CRS SynchroDivider}!RCC\_CRS\_SYNC\_DIV8@{RCC\_CRS\_SYNC\_DIV8}}
\index{RCC\_CRS\_SYNC\_DIV8@{RCC\_CRS\_SYNC\_DIV8}!RCCEx CRS SynchroDivider@{RCCEx CRS SynchroDivider}}
\doxysubsubsubsubsubsection{\texorpdfstring{RCC\_CRS\_SYNC\_DIV8}{RCC\_CRS\_SYNC\_DIV8}}
{\footnotesize\ttfamily \label{group___r_c_c_ex___c_r_s___synchro_divider_gad2bd5dac3b5d22a86bc3c8d9a355768a} 
\#define RCC\+\_\+\+CRS\+\_\+\+SYNC\+\_\+\+DIV8~(\mbox{\hyperlink{group___peripheral___registers___bits___definition_gae595c852cabc78e8bc9055625d68ca54}{CRS\+\_\+\+CFGR\+\_\+\+SYNCDIV\+\_\+1}} \texorpdfstring{$\vert$}{|} \mbox{\hyperlink{group___peripheral___registers___bits___definition_ga386136633d2d7330e0ac5ca183c292de}{CRS\+\_\+\+CFGR\+\_\+\+SYNCDIV\+\_\+0}})}

Synchro Signal divided by 8 